The present invention relates to a manufacturing method for a semiconductor device, and more particularly, to a method for isolating elements of a semiconductor device by means of trenches and the local oxidation of silicon (LOCOS), so as to be usefully applied to highly integrated memory devices and to improve the electrical characteristics of the elements.
The electrical isolation of each element formed on a silicon wafer is needed in the large-scale integration of chips. Recently, techniques for reducing the width of an isolation area and the size of each element formed on a semiconductor wafer have been developed as semiconductor devices become more integrated. The development of techniques to isolate semiconductor elements on a wafer from one another is becoming very important in competition among semiconductor manufacturers.
A junction isolation method for isolating bipolar-type elements was developed in the early days of the semiconductor industry, when bipolar-type integrated circuits first entered main stream use. Although the junction isolation method is very simple, the element isolation area is relatively large. Thus, this method is actually an obstacle in increasing integration, and lowers the circuit's operating speed due to a resulting high parasitic capacitance.
Additionally, a MOS transistor has been developed with a structure entirely different from that of a bipolar-type transistor. Accordingly, an element isolation structure different from the above junction isolation method is required. Under these circumstances, a LOCOS method is utilized which forms a semi-recessed oxide in a non-active region (field region) of a substrate.
The above-noted LOCOS method is widely used due its many merits, which include a reduced junction capacity, reduced parasitic effects, ease of self alignment processing and reduced spreading in the transverse direction in comparison with the conventional junction isolation method. However, the conventional LOCOS method also has drawbacks: (a) a great deal of field oxide permeates the element active region to thereby form an undesirable bird's beak structure, (b) the application of sub micron lithography techniques is difficult due to flexion of the surface, and (c) due to the long-term oxidation, the re-distribution of impurities results in certain unwanted defects. To overcome these drawbacks of the LOCOS method, many modified LOCOS methods have been proposed. Some examples of these modified LOCOS methods are: (1) a method of forming a field oxide by oxidizing the recessed part of a substrate, (2) an etched-back LOCOS method that etches back a part of the field oxide so as to reduce the bird's beak and gain a more planarized surface after the field oxide is grown, (3) a method of using a poly-buffer pad film (poly 50 nm/oxide film 5-10 nm) and a nitride film (100-240 nm) instead of using a common pad oxide film, (4) a sealed interface local oxidation (SILO) method that forms a silicon nitride film directly on a silicon substrate prior to the formation of the pad oxide film, and (5) a sidewall-masked isolation (SWAMI) technique that uses a sidewall mask. However, even though various modified LOCOS methods may be used, there is a limit to reducing the isolation region, due to the presence of the bird's beak. Also, the partial oxidation processing stresses the semiconductor wafer which degrades junction characteristics and thereby diminishes a DRAM's refresh characteristic.
Besides the above modified LOCOS methods, methods of isolating the element without partially oxidizing the semiconductor substrate have also been proposed. Examples of such include a trench isolation method and a selective epitaxial isolation method.
The trench isolation method calls for forming a trench in the semiconductor wafer and then filling the trench with polysilicon or insulating material so as to isolate an element. This method can reduce both parasitic capacitance and the isolation region of the element.
However, since the ultimate surface shape of the filling material varies depending on the trench size, the general trench isolation method results in poor step coverage by a subsequent film stacked on the filling material. Specifically, when a MOS element is formed in an active region such that a gate electrode of the MOS element extends so as to traverse the trench, a signal can be delayed due to the poor step coverage of the trench. In addition, a narrow trench is filled excessively in order to sufficiently fill the wide trench, which causes difficulty in planarization. Generally, since the width of the element isolation region formed in a semiconductor wafer is irregular, the trench element isolation technique is unsuitable as a replacement for the conventional LOCOS method when trenches of differing widths are to be formed.
To overcome the above drawbacks of the trench isolation method, a double trench isolation (DTI) method has been proposed, which forms a trench having a certain width and depth around the isolation region, and then fills the trench with an insulating material to form an element isolation region. For example, Korean Patent laid open publication No. 92- 702022 (PCT Application No. PCT/JP 90/01321 by Masshita Ikuya) discloses an isolation method, accomplished by forming a groove between the element active region and the element isolation region of the semiconductor wafer, in order to provide an element isolation technique by means of a trench which permits a good element isolation characteristic and a planarized surface of the element isolation region, without regard to the width of the element isolation region.
FIG. 1 to FIG. 6 are schematic representations showing the conventional method in the above Korean Patent laid open publication.
FIG. 1 shows a step of forming a multi-layer pattern to define an active region on the semiconductor wafer. More specifically, a tri-layer which comprises a first silicon nitride film 102, a first silicon oxide film 103 and a second silicon nitride film 104 is formed on a semiconductor wafer 101, and a photoresist pattern 105 is formed in the element formation region of semiconductor wafer 101. Then, etching the tri-layer using photoresist pattern 105 forms a tri-layer pattern.
FIG. 2 shows a step of forming a spacer on the sidewalls of the tri-layer pattern, and forming grooves in portions which will be isolation regions of the semiconductor wafer using the spacer. That is, photoresist pattern 105 is removed and a third silicon nitride film is deposited on the wafer, on which the pattern of the above tri-layer is formed, which then is anisotropically etched so as to form a third silicon nitride spacer 106. Then, the exposed portions semiconductor wafer 101 is anisotropically etched and first grooves 107 are formed, using second silicon nitride film 104 and a third silicon nitride spacer 106 as etching masks.
FIG. 3 shows a step of filling first grooves 107 with a second silicon oxide film 108, and depositing a photoresist so as to form a photo- resist pattern 109 in an element isolation region, over which a third silicon oxide film 110 is then formed.
FIG. 4 shows a step of etching back third silicon oxide film 110 and a second silicon oxide film 108. Then, photoresist pattern 109 is removed.
FIG. 5 shows a step of an anisotropically etching of the semiconductor wafer 101 which is exposed by removing second silicon nitride film 104 and third silicon nitride film spacer 106. Here, second grooves 111 are formed by removing third silicon nitride spacer 106 and etching the exposed semiconductor wafer, using first and second silicon oxide films 103 and 108 as masks.
FIG. 6 shows a step of growing a thin oxide film 112 on the whole surface of the resultant structure including second grooves 111, and filling second grooves 111 with a polysilicon 113 by a deposition. Then, an upper part of polysilicon 113 is oxidized and the resultant structure is etched back so as to expose semiconductor wafer 101, as seen in FIG. 6.
According to the above method, since first silicon nitride film 102 is formed directly on semiconductor wafer 101, a pit is generated and the quality of the gate oxide film which is to be formed in subsequent processing is lowered. Additionally, when second grooves 111 are filled with polysilicon 113, a hump is generated in the boundary between the groove and the active region due to a step occurring between them. Therefore, electrical characteristics of the transistor are degraded, and the polysilicon which fills a grooves 111 and the polysilicon of the gate electrode are apt to make direct contact with each other. If they do not contact directly, the thickness of the gate oxide film therebetween is too thin to maintain suitable insulation characteristics.
Meanwhile, commonly owned U.S. Pat. application Ser. No. 07/955,108 now (application Pat. No. 5,308,784, date: 1 Oct. 1, 1992 by Y. K. Kim et al.) having a similar purpose with that of the above-described Ikuya et al. disclosure, combines the aforementioned double trench isolation method with the LOCOS method to form a trench isolation structure between the element active region and element isolation region. Here, a field oxide film is formed in the center of the element isolation region by the LOCOS method. By the above invention of Kim et al. (also the inventors of the present invention), the surface of the element isolation region is planarized without regard to the width of the element isolation region to thus form an element isolation well.
FIGS. 7 to 12 illustrate the element isolation method disclosed in the aforementioned U.S. patent application Ser. No. 07/955,108. Now U.S. Pat. No. 5,308,784
FIG. 7 is a sectional view showing a step of forming a multi-layer pattern which has an a aperture to define an element isolation region on a semiconductor wafer. That is, a pad oxide film 121, a nitride film 122 and a high temperature oxide (HTO) film 123 are sequentially formed on semiconductor wafer 120 to predetermined thicknesses, and then a photoresist layer is deposited. After that, a photoresist pattern 124 is formed to define non-active region for etching the exposed pad oxide film 121, nitride film 122, and HTO film 123. A dry etching like reactive ion etching (RIE) is continued until a portion of semiconductor wafer 120 is exposed. An aperture 125 is thereby formed.
FIG. 8 is a sectional view showing a step in which photoresist pattern 124 is removed and a spacer is formed on the sidewalls of aperture 125. In more detail, photoresist pattern 124 for forming aperture 125 is removed. Thereafter, a silicon nitride film or polysilicon is deposited on the entire surface of the wafer, and then is anisotropically etched so as to form a spacer 126 on the sidewall of aperture 125. At this moment, semiconductor wafer 120 is exposed via the aperture 125, which is further defined by spacer 126.
Then, a thermal oxidation is performed in the wafer region and the silicon in the portion of the semiconductor wafer exposed through aperture 125 is consumed toward the wafer direction, which gradually forms a thermal oxide layer. As a result, a thermal oxide film 127 extends below the wafer's surface and has a width is somewhat wider than the region defined by the spacer 126.
FIG. 9 is a sectional diagram showing a step of forming a trench along the sidewalls of an element isolation region. In more detail, spacer 126 formed on the sidewalls of the aperture 125 is dry-etched and removed. Then, by dry etching, trenches 128, 129 having a predetermined depth and width are formed in the exposed wafer along the boundaries of the non-active region, adjacent thermal oxide film 127.
FIG. 10 is a sectional view showing a step of exposing the wafer by dry-etching and removing the thermal oxide film 127 which functioned as a trench buffer layer after trenches 128, 129 were formed. At this time, a flat wafer surface having a pre-determined depth with respect to the surface of the wafer within the aperture is realized as shown in FIG. 10.
FIG. 11 is a sectional view showing a step of filling the inside of trenches 128, 129 with proper insulating materials. That is, thermal oxidation is performed on the exposed wafer, such that the trenches are filled with a thermal oxide film 130. At this time, the thermal oxide film 130 penetrates only slightly into wafer 120, as shown by the dotted lines in FIG. 11.
FIG. 12 is a sectional view showing a step of completing the element isolation region in wafer 120. That is, when the pad oxide film 121 and a nitride film 122 are removed by wet etching in order to expose the active region, an element isolation region having a certain element isolation width 131 is completed on semiconductor wafer 120.
Since the boundary of an element isolation region is fixed by a trench in the disclosed element isolation method (U.S. application Ser. No. 07/955,108), now U.S. Pat. No. 5,308,784 an element isolation technique without regard to the width of an element isolation region can be applied. Further, the element isolation region has a planarized surface, which avoids signal delay caused by the conventionally poor step coverage in a metal wiring between active regions. In addition, short circuits which have conventionally occurred in wiring due to the poor step coverage do not occur.
However, in the disclosed element isolation method, when a nitride film spacer 126 is removed, it is hard to distinguish nitride spacer 126 from nitride film 122 of aperture pattern, which then causes difficulty in precise etching. Besides a limitation of the resolution of photo-lithography techniques, a thermal oxide film (reference numeral 130 in FIG. 11) penetrates the active region during the thermal oxidation processing for filling trenches 128 and 129, which establishes a 0.5 .mu.m-wide element isolation region and thereby impedes high integration. Additionally, a great deal of lateral stress is generated in the boundary between the trench and the active region.